000087204 001__ 87204
000087204 005__ 20190316233750.0
000087204 02470 $$2DAR$$a7028
000087204 02470 $$2ISI$$a000230363100008
000087204 037__ $$aARTICLE
000087204 245__ $$aProcessor Enhancements for Media Streaming Applications
000087204 269__ $$a2005
000087204 260__ $$c2005
000087204 336__ $$aJournal Articles
000087204 520__ $$aThe development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware / software codesign methodology.
000087204 6531_ $$acodesign
000087204 6531_ $$ahardware design space exploration
000087204 6531_ $$aLTS1
000087204 6531_ $$aLTS2
000087204 6531_ $$amatching pursuit
000087204 6531_ $$amultimedia processing
000087204 6531_ $$areconfigurable coprocessor
000087204 6531_ $$asoftware profiling
000087204 6531_ $$avideo coding
000087204 6531_ $$aLTS2
000087204 700__ $$0241303$$g152671$$aBilavarn, S.
000087204 700__ $$0241304$$g113757$$aDebes, E.
000087204 700__ $$aVandergheynst, P.$$g120906$$0240428
000087204 700__ $$aDiguet, J.
000087204 773__ $$j41$$tJournal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology$$k2
000087204 8564_ $$uhttps://infoscience.epfl.ch/record/87204/files/Bilavarn2005_1158.ps$$zn/a$$s5719248
000087204 909C0 $$xU10380$$0252392$$pLTS2
000087204 909CO $$qGLOBAL_SET$$pSTI$$ooai:infoscience.tind.io:87204$$particle
000087204 937__ $$aEPFL-ARTICLE-87204
000087204 970__ $$aBilavarn2005_1158/LTS
000087204 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000087204 980__ $$aARTICLE