000087142 001__ 87142
000087142 005__ 20190316233748.0
000087142 02470 $$2ISI$$a000225567800126
000087142 037__ $$aCONF
000087142 245__ $$aReconfigurable Coprocessor for Media Streaming
000087142 269__ $$a2004
000087142 260__ $$bSPIE$$c2004
000087142 336__ $$aConference Papers
000087142 490__ $$aProc. of the IEEE Int. Conf. on Multimedia and Expo
000087142 520__ $$aThe development of more processing demanding video standards on one hand and the popularity of mobile devices such as digital cameras or wireless videophones on the other hand introduce a need of optimization at the processor level. Reconfigurable systems provide an interesting answer to this problem and several works have explored the possibility of performance and power optimization. The following study focusses on tuning a reconfigurable hardware to the requirements of future media processing, using DSP operators appeared in recent FPGA families as an alternative to the typical ALU based architectures. In this paper, architecture perspectives are proposed with respect to low cost development constraints, backward compatibility, easy coprocessor usage and power / performance enhancement, using a new scalable data representation optimized for Quality of Services (Matching Pursuit 3D algorithms).
000087142 6531_ $$aLTS1
000087142 6531_ $$aLTS2
000087142 6531_ $$aMatching Pursuit
000087142 6531_ $$aperformance / power optimization
000087142 6531_ $$aReconfigurable coprocessor
000087142 6531_ $$aLTS2
000087142 700__ $$0241303$$g152671$$aBilavarn, S.
000087142 700__ $$aDebes, E.$$g113757$$0241304
000087142 773__ $$tICME
000087142 8564_ $$uhttps://infoscience.epfl.ch/record/87142/files/Bilavarn2004_1170.ps$$zn/a$$s1834172
000087142 909C0 $$xU10380$$0252392$$pLTS2
000087142 909CO $$ooai:infoscience.tind.io:87142$$qGLOBAL_SET$$pconf$$pSTI
000087142 937__ $$aEPFL-CONF-87142
000087142 970__ $$aBilavarn2004_1170/LTS
000087142 973__ $$sPUBLISHED$$aEPFL
000087142 980__ $$aCONF