Rapid evaluation and design space exploration at the algo­rithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural es­timation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the tar­get reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) com­ponents for a 2D DWT and a speech coder lead to an aver­age error of about 10 % for temporal values and 18 % for area estimations.