Fast Prototyping of Reconfigurable Architectures: An Estimation and Exploration Methodology from System-Level Specifications

Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural estimation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the target reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) components for a 2D DWT and a speech coder lead to an average error of about 10 % for temporal values and 18 % for area estimations.


Published in:
ACM international Symposium on Field-Profgrammable Gate Arrays
Year:
2003
Publisher:
SPIE
Keywords:
Laboratories:




 Record created 2006-06-14, last modified 2018-01-27

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