MONOLITHIC INTEGRATION OF NANOMECHANICAL RESONATORS WITH CMOS CIRCUITRY: FULL-WAFER NANOPATTERNING BY NANOSTENCIL LITHOGRAPHY

For the purpose of integrating nanomechanical structures with CMOS circuitry, nanostencil lithography ensures parallel patterning for rapid processing at wafer scale and nanometer-sized features definition. Moreover, this patterning technique is compatible with CMOS substrates given that it does not alter circuitry performance. However, a major limitation in nanostencil lithography is gap-induced pattern blurring naturally occurring if a planar stencil is used in combination with a substrate containing topography (e.g. CMOS). This phenomenon has been characterized and a corrective technique is implemented in order to eliminate the blurring.


Year:
2006
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Note: The status of this file is: EPFL only


 Record created 2006-03-20, last modified 2018-03-17

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