Routage detaillé de circuits integrés par recuit simulé
In this paper we present an application of simulated annealing to the detailed routing of integrated circuits. This application is based on local modifications to a simple, but generally inacceptable, initial configuration. The new configurations so generated are evaluated through a cost function incorporating strong penalties for the illegal situations. The results are satisfactory, but we are still studying the algorithm behaviour as a function of its parameters.
Record created on 2006-02-13, modified on 2016-08-08