Journal article

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with imposed time constraints. Design and implementation of a very low power, low phase noise, wide tuning range oscillator, and a very high-efficiency adaptive bias regulator block is proposed for battery operated equipment. The proposed design allows implementation of an adaptive bias/clock generator operating at 1 Volt supply voltage. Implemented in 0.18um CMOS technology, operating at 50MHz to 250MHz, the proposed clock generator (based on voltage controlled ring oscillator, VCO) has a tuning range of almost 50%. At 125MHz, the phase noise of the VCO is -98dBc/Hz @1MHz offset from the carrier. Adaptive bias generator, implemented in same process has an efficiency of 96.5%. The silicon area of the designed adaptive bias/clock generator block is 35um by 95um, consuming very low power, 0.41mW. Hence, the proposed adaptive bias/clock generator block with its emphasized properties is a good candidate that can be used local to the processing element in portable, battery-operated applications subject to DVS.


    • LSM-ARTICLE-2005-005

    Record created on 2005-12-07, modified on 2017-05-10


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