Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with imposed time constraints. Design and implementation of a very low power, low phase noise, wide tuning range oscillator, and a very high-efficiency adaptive bias regulator block is proposed for battery operated equipment. The proposed design allows implementation of an adaptive bias/clock generator operating at 1Volt supply voltage. Implemented in 0.18um CMOS technology, operating at 50MHz to 250MHz, the proposed clock generator (based on voltage controlled ring oscillator, VCO) has a tuning range of almost 50%. At 125MHz, the phase noise of the VCO is -98dBc/Hz @1MHz offset from the carrier. Adaptive bias generator, implemented in same process has an efficiency of 96.5%. The silicon area of the designed adaptive bias/clock generator block is 35um by 95um, consuming very low power, 0.41mW.

Published in:
Proceedings of PhD Research in Microelectronics and Electronics (PRIME), 2, 359 - 362
Presented at:
PhD Research In Microelectronics and Electronics (PRIME), Lausanne, Switzerland, July 25-28

 Record created 2005-12-07, last modified 2018-03-17

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