A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology
Tajalli, Armin; Muller, Paul; Atarodi, Mojtaba; Leblebici, Yusuf
2005

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Abstract

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18µm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045µm2 silicon area.

Details

Title A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology
Author(s) Tajalli, Armin ; Muller, Paul ; Atarodi, Mojtaba ; Leblebici, Yusuf
Published in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC)
Pages 193-196
Conference 31st European Solid-State Circuits Conference ESSCIRC, Grenoble, France, September 12-16
Date 2005
Keywords
DOI https://doi.org/10.1109/ESSCIR.2005.1541592
Laboratories LSM
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2005-12-06

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