Analysis of Error Recovery Schemes for Networks on Chips
Murali, Srinivasan; Benini, Luca; Theocharides, Theocharis; Vijaykrishnan, N.; Irwin, Mary Jane; De Micheli, Giovanni
2005

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Abstract

In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.

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Title Analysis of Error Recovery Schemes for Networks on Chips
Author(s) Murali, Srinivasan ; Benini, Luca ; Theocharides, Theocharis ; Vijaykrishnan, N. ; Irwin, Mary Jane ; De Micheli, Giovanni
Published in IEEE Design & Test of Computers
Volume 22
Issue 5
Pages 434-442
Date 2005
Publisher Institute of Electrical and Electronics Engineers
DOI https://doi.org/10.1109/MDT.2005.104
Other identifier(s) DAR: 7533
View record in Web of Science
Laboratories LSI1
Record Appears in Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Peer-reviewed publications
Work outside EPFL
Journal Articles
Published
Record creation date 2005-11-07

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