Analysis of Error Recovery Schemes for Networks on Chips

Murali, Srinivasan; Benini, Luca; Theocharides, Theocharis; Vijaykrishnan, N.; Irwin, Mary Jane; De Micheli, Giovanni

doi:10.1109/MDT.2005.104

research article

Analysis of Error Recovery Schemes for Networks on Chips

Murali, Srinivasan

•

Benini, Luca

•

Theocharides, Theocharis

2005

IEEE Design & Test of Computers

In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.

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Murali, S., Benini, L., Theocharides, T., Vijaykrishnan, N., Irwin, M. J., & De Micheli, G. (2005). Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design & Test of Computers, 22(5), 434–442. https://doi.org/10.1109/MDT.2005.104

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