Analysis of Error Recovery Schemes for Networks on Chips

In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.


Published in:
IEEE Design & Test of Computers, 22, 5, 434-442
Year:
2005
Publisher:
Institute of Electrical and Electronics Engineers
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 Record created 2005-11-07, last modified 2018-03-17

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