Design, Synthesis, and Test of Network on Chips

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.


Published in:
IEEE Design & Test of Computers, 22, 5, 404-413
Year:
2005
Laboratories:




 Record created 2005-11-07, last modified 2018-03-17

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