A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for a-priori functional fault tolerance analysis was developed. It is a statistical Monte Carlo based tool that induces different failure models, and does subsequent evaluation of system reliability under realistic constraints. A structured fault modeling architecture is also proposed, which is together with the tool a part of the new design method representing a compatible improvement of existing IC design methodologies.


Published in:
Proceedings of the IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC), 199-204
Presented at:
IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC), Perth, Australia, October 17-19
Year:
2005
Publisher:
IFIP
Keywords:
Laboratories:




 Record created 2005-10-25, last modified 2018-03-17

n/a:
Download fulltextPDF
External link:
Download fulltextURL
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)