Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data jitter and its effects on the recovered data bit error rate using Matlab. The second method is based on time-domain simulation using VHDL and VHDL-AMS, where the bit-error rate is estimated based on the eye opening in the eye diagram.


Published in:
Proceedings of the Forum on Specification and Design Languages (FDL)
Presented at:
Forum on Specification and Design Languages (FDL), Lausanne, Switzerland, September 27-30
Year:
2005
Keywords:
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 Record created 2005-10-10, last modified 2018-03-17

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