A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering
2000
Files
Details
Title
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering
Author(s)
Hatirnaz, I. ; Leblebici, Y.
Published in
2000 IEEE International Symposium on Circuits and Systems (ISCAS)
Volume
4
Pages
685-688
Conference
2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, May 2000
Date
2000
Laboratories
LSM
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Conference Papers
Work produced at EPFL
Published
Conference Papers
Work produced at EPFL
Published
Record creation date
2005-08-30