Design and Realization of a 2.4 Gbps - 3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology
2003
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Details
Title
Design and Realization of a 2.4 Gbps - 3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology
Author(s)
Gursoy, Z. O. ; Leblebici, Y.
Published in
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings
Pages
99-102
Conference
IEEE International SOC Conference 2003, Portland, September 2003
Date
2003
Laboratories
LSM
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Conference Papers
Work produced at EPFL
Published
Conference Papers
Work produced at EPFL
Published
Record creation date
2005-08-30