Infoscience

Conference paper

Design and Realization of a 2.4 Gbps - 3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology

    Note:

    IEEE International SOC Conference 2003, Portland, September 2003

    Reference

    • LSM-CONF-2003-011

    Record created on 2005-08-30, modified on 2016-08-08

Related material