A Novel Circuit-Level Fault-Tolerance Concept for Boolean Gates Using Low-Yield Nanometer-Scale Transistors


Presented at:
2004 International Joint Conference on Neural Networks, Budapest, July 2004
Year:
2004
Note:
2004 International Joint Conference on Neural Networks, Budapest, July 2004
Laboratories:




 Record created 2005-08-30, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)