Infoscience

Conference paper

A Novel Circuit-Level Fault-Tolerance Concept for Boolean Gates Using Low-Yield Nanometer-Scale Transistors

    Note:

    2004 International Joint Conference on Neural Networks, Budapest, July 2004

    Reference

    • LSM-CONF-2004-013

    Record created on 2005-08-30, modified on 2016-08-08

Fulltext

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