Infoscience

Conference paper

A Highly Fault Tolerant PLA Architecture for

    Note:

    Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT'04, Cannes, France, October 2004

    Reference

    • LSM-CONF-2004-008

    Record created on 2005-08-30, modified on 2016-08-08

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