A Highly Fault Tolerant PLA Architecture for


Year:
2004
Note:
Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT'04, Cannes, France, October 2004
Laboratories:




 Record created 2005-08-30, last modified 2018-03-17

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