GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator
1996
Details
Title
GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator
Author(s)
Ienne, Paolo ; Viredaz, Marc A.
Published in
Neural Networks Theory, Technology, and Applications
Editor(s)
Series
Technology Update Series
Pages
797-808
Date
1996
Publisher
New York, IEEE
Note
Reprinted from citeIenneOct93asap.
Laboratories
LAP
Record Appears in
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Work produced at EPFL
Book chapters
Published
Work produced at EPFL
Book chapters
Published
Record creation date
2005-08-08