Home > GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator
 

GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator

Ienne, Paolo ; Viredaz, Marc A. ; Dadda, Luigi ; Wah, Benjamin

Published in:
Proceedings of the International Conference on Application Specific Array Processors, 345-56
Year:
1993
Note:
Reprinted in citeIenne96asap.
Laboratories:
LAP

Record appears in:
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Conference Papers
Work produced at EPFL
Published



 Record created 2005-08-08, last modified 2018-03-17


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