Performance Driven Reliable Link Design for Networks on Chips

With decreasing feature size of transistors, the interconnect wire delay is becoming a major bottleneck in current Systems on Chips (SoCs). Another effect of shrinking feature size is that the wires are becoming unrealable as they are increasingly susceptible to various noise sources such as cross-talk, coupling noise, soft errors etc. Increasing importance of wire delay an reliability has lead to a communication centric design approach, Networks in Chip (NoC), for building complex SoCs. Current NoC communication design methodologies are based on conservative design approaches and consider worst case operating conditions for link design, resulting in lare latency penalty for data transmission. In order to substantially descrease the link delay and therby increase system performance an aggressive design approach is needed. In this work we present Terror, timing error tolerant communication system, for aggressively design the links of NoCs. In our methodology, instead of avoiding timing errors by worst-case design, we do aggressive design by tolerating timing errors. Simulation results show large latency savings (up to 35%) for the Terror based system compared to traditional design methodology.

Published in:
Proceedings of the 10th Asia and South Pacific Design Automation Conference (ASP-DAC 2005), 2, 749-754
Presented at:
10th Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, January 18-21, 2005

 Record created 2005-07-29, last modified 2018-03-17

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