High voltage devices for standard MOS technologies: characterisation and modelling
This work reports on the analysis of high voltage lateral devices. Two different architectures, self-aligned LDMOS and non-self-aligned XDMOS are presented and used in this work. For the separation of the physical effects that take place inside the HV devices the intrinsic drain voltage concept (VK) is proposed. The variation of VK is explained and related to the physical effects inside the device and the charge variation. Through the K point potential, the analysis of the channel and drift resistances is performed function of VG and VD for the whole voltage domain. The several orders of magnitude variation of the resistances is explained by the turning off-on of the intrinsic MOS transistor and also by the depletion of the drift part. The capacitances variation function of the gate voltage, for different drain voltages is discussed in detail taking into account the charge repartition inside the device. It is revealed that the charge transfer between the intrinsic MOSFET and the drift part impacts on the capacitances behaviour resulting in specific peaks on CGS+CGB and CGD characteristics function of VG. The correlation between the capacitances variation and the intrinsic drain voltage VK is demonstrated and it is shown that the formation of the conductive channel in the drift zone is responsible for the decrease of both VK potential and capacitances. A geometrical approximation of the drift zone is presented for the modelling purposes of the HV devices. The electrical approximations that have to be taken into account to build the DC model are also explained. The convergence is granted for the whole voltage domain and no discontinuities were observed for all derivatives. The SMARTSPICE model implementation is compared to the measurements obtained on 100V devices provided by AMI Semiconductor. The accuracy at room temperature shows a RMS error which is less than 6% for the whole voltage domain. The good accuracy of the model is also verified for external temperature variations form room temperature up to 150°C. The scalability of the model for different widths ranging form 10µm up to 250µm is also confirmed. Finally, the impact of self-heating effect on HV devices is clearly studied in these devices. A novel method for the extraction of both RTH and CTH, accounting for the temperature dependence of the thermal resistance, is proposed and validated. The accuracy of the method is verified by calibrated SPICE simulations. The proposed extraction of parasitic thermal network (RTH, CTH) is independent on the device architecture and can be used in any type of HV MOSFETs.
Faculté des sciences et techniques de l'ingénieur
Institut de microélectronique et microsystèmes
Laboratoire d'électronique générale 2
Jury: Michel Declercq, Yusuf Leblebici, Christian Maier, Radivoje Popovic, Florin Udrea
Public defense: 2004-12-10
Record created on 2005-03-16, modified on 2016-10-18