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Conventional RF power amplifiers usually give their maximum efficiency near the maximum output power level. When the output power decreases, the efficiency drops sharply. Deep class AB or B PAs improve their efficiency by a self-adaptation of the current drawn from the power supply. However, in many cases, both deep class AB and B do not provide enough linearity like, for instance, in CDMA applications where spectral re-growth is of first concern. From class A to class B, RF PAs face the linearity-efficiency trade-off. The class A is linear but power inefficient, whereas class B is efficient but has a poor linearity. An alternative to the linearity-efficiency trade-off is to dynamically adapt the power supply voltage of a linear PA with respect to the instantaneous envelope value of the modulating signal. The linear PA is of class A or class AB and its collector or drain voltage is adapted to avoid RF output voltage to saturate such that, ideally, the linearity is not degraded. The supply voltage adaptation should be capable to follow large envelope bandwidth for CDMA application (3.8MHz for UMTS and 1.2MHz for IS-95). This thesis work treats System and modulator design aspects. System aspects covers mainly the PA bias influence on the system linearity and system simulation issues. The modulator design covers the architecture aspect to address bandwidth and efficiency requirements and the design in a CMOS 0.35µm process. The modulator is a fast high efficiency step down converter providing all necessary functions to transform the main power supply according to the low envelope detected level into a varying supply for an external PA. The typical carrier frequency is around 1900MHz with a typical minimum level of 100µW whereas the PA power consumption is in the order of a couple of hundred milliwatts.