Conception d'un émetteur-récepteur à faible consommation intégré en technologie CMOS

This thesis aims at developing wireless systems with a strong emphasis on low-power consumption and low-voltage operation. The main technical objective is the development of a single cells battery operated fully integrated CMOS RF transceiver that fulfills the main common requirements of low bit rate (typically a few 20 kbits/s) distributed wireless remote sensing Microsystems. The radio link should be bi-directional (half-duplex), work on small distances (maximum 100 m) and operate in the 434 MHz ISM band. The single chip transceiver is designed for specific applications such as home automation systems, security and surveillance systems, remote medical care and monitoring, computer interactive interfaces and robotics. In order to reduce power consumption, avoid DC-DC converters and be ready for next-generation deep-submicron processes with limited supply voltage, single battery operation is desirable. Therefore, ultimately, the circuits should be able to operate with a supply as low as 1V, corresponding to the end-of-life battery voltage. Flicker noise rejection, power consumption due to the dynamic range or due to the high frequency, low voltage and low current density constraints are the main theoretical aspects discussed in this thesis. The integrated blocks are the low noise amplifier, the mixers, the power amplifier, the modulation and demodulation path. A direct conversion architecture is chosen in order to minimize the number of external components, allow for a reduced quadrature accuracy of the LO signal as well as to optimize the power consumption. A test chip containing the complete transceiver is designed and integrated in a 0.5 µm standard digital CMOS process. The working frequency is the 434MHz ISM Band and the modulation scheme is a wide band FSK with a frequency deviation of 100kHz. The complete receiver, including signal path and frequency synthesizer, operates with only 1V supply voltage. It achieves a -95dBm sensitivity at 1/1000 of BER for a data rate of 24kbits/s and an ultra low power consumption of only 1mW. The complete transmitter achieves an overall efficiency higher than 38% for a 1.2V supply voltage and an output power reaching 10dBm. The output power is controlled digitally between ldBm and 10dBm by steps of 3dB.

    Thèse École polytechnique fédérale de Lausanne EPFL, n° 2231 (2000)
    Faculté des sciences et techniques de l'ingénieur
    Jury: Jean-Dominique Decotignie, Qiuting Huang, Andreas Kaiser, Philippe Robert

    Public defense: 2000-9-8


    Record created on 2005-03-16, modified on 2016-08-08

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