Programmable VLSI systolic processors for neural network and matrix computations
1996
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Title
Programmable VLSI systolic processors for neural network and matrix computations
Author(s)
Ienne Lopez, Paolo
Advisor(s)
Pagination
159
Date
1996
Publisher
Lausanne, EPFL
Language
English
Laboratories
LAP
Record Appears in
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Scientific production and competences > EPFL Theses
Work produced at EPFL
Published
Theses
Scientific production and competences > EPFL Theses
Work produced at EPFL
Published
Theses
Record creation date
2005-03-16