A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) operatively connected to the track-and-hold switch and configured to receive the sampled input voltage from the track-and-hold switch, redistribute the sampled charge based on a digital code received from an asynchronous successive approximation logic circuit, and output the voltage corresponding to the manipulated sampled charge; a comparator configured to resolve the sign of the voltage on the capacitive digital-to-analog converter and output a decision. The asynchronous successive approximation logic circuit is operatively connected to the comparator and configured to implement the successive approximation algorithm by supplying the digital code to the capacitive digital-to-analog converter for redistributing the sampled charge depending on the decision from the comparator. The capacitive digital-to- analog converter comprises a constant common-mode switching logic.