With the increasing capabilities of the microelectronics technology, future particle detectors in high energy physics will be able to yield high-level features that are not only simple geometrical positions or energy measurement in the silicon sensors used, but also high-level primitives. The ability to compute such high-level primitives in near real-time is what we characterize as "intelligence" and will allow constructing detectors with novel functionalities and easing the offline analysis in experiments to handle immediately more complex features of the measurements. This thesis presents a novel approach adopted for the development of silicon sensor detectors capable of rejecting locally signals from low transverse momentum. The basic concept consists of correlating signals in two closely-spaced sensors. The readout and control electronics for these type of sensors require the development of a set of ASICs that incorporate dedicated specialized signal processing techniques, generating in real-time trigger primitives and transmitting them to the Level-1 (L1) central trigger system, while, at the same time, transmitting the L1 triggered data to the detector readout system. In order to exploit the full bandwidth of the optical fiber transmission links, it is necessary to implement a data concentrator ASIC, called CIC (Concentrator IC). The thesis focuses on system level studies needed to assist and develop the CIC ASIC architecture. In this context, system level simulations and modeling with modern EDA tools have been employed to optimize the readout chain and set synchronization techniques for the interconnects with the readout ASICs. The thesis describes also the CIC ASIC architecture and the prototype results to evaluate final performances. The developed CIC ASIC should be able to operate within a very tight power budget and in a radiation environment of 100 Mrad. Radiation tolerance design techniques have been employed in order to mitigate the effects of Total Ionizing Dose as well as of Single Event Upsets. For the implementation of the readout ASICs it is proposed to use a 65 nm CMOS process.