In this work, we present the investigation of the combination of p-GaN gate and tri-gate structures to achieve normally-off operation on GaN-on-Si MOSFETs. We have developed and optimized a selective and low-damage p-GaN etching recipe to stop at the AlGaN barrier and minimize the degradation in on-resistance (R ON ). The p-GaN length and tri-gate filling factor (FF) were optimized to achieve a good trade-off between high threshold voltage (V TH ) and low R ON . The excellent channel control capability offered by tri-gate structure led to a reduced OFF-state leakage current (I OFF ), higher ON/OFF ratio, smaller sub-threshold slope (SS) compared to similar planar p-GaN devices. These results unveil the excellent prospects of p-GaN tri-gate technology for future power electronics applications.