Analysis of Large-Signal Output Capacitance of Transistors using Sawyer–Tower Circuit

A detailed analysis on the Sawyer–Tower method used in the measurement of large-signal output capacitance (Co) of power transistors is presented, followed by important design recommendations to obtain accurate results. Key factors affecting the proper implementation of the technique, such as power amplifier characteristics, load slew-rate, reference capacitor (Cref) and reverse conduction of the device are addressed, with accompanying simulation and experimental results for Si, SiC and GaN devices. A thorough investigation on the selection of Cref is presented, with a new equation to correctly determine its value for a given voltage swing and output capacitance range of the Device Under Test (DUT). We report that the Sawyer– Tower circuit impose the DUT to enter steady-state reverse conduction under certain conditions, leading to charge-voltage (QV) hysteresis patterns unrelated to Co. Our analysis reveals that the origin of this phenomenon is related to DUT’s leakage current, and that it could be minimized by proper selection of the excitation frequency. This work intends to provide an effective guide on designing and using the Sawyer–Tower circuit and to induce further scientific insight in characterizing Co.


Published in:
IEEE Journal of Emerging and Selected Topics in Power Electronics, 1-1
Year:
May 06 2020
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 Record created 2020-05-10, last modified 2020-05-11

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