Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control

We propose and experimentally demonstrate double-gated n-type WSe 2 FETs with excellent top gate high-k dielectric layer. Under back gate control, the devices behave as n-type enhancement transistors, with ON/OFF current ratios larger than 6 orders of magnitude and a ON current close to 1 pA/μm under a drain bias of 100 mV. Negative top gate biases determine a much steeper turn-on of the back gated transfer characteristic and a reduction of the hysteresis. Top gated device behaves as n-type depletion FETs, exhibiting a I ON /I OFF ratio larger than 10 6 under positive bias applied to the back gate. A minimum hysteresis of 40 mV and an average subthreshold slope close to 100 mV/dec prove the high quality of the deposited top gate dielectric. The electron mobility has been extracted using the Y-function method, obtaining 22.15 cm 2 V -1 s -1 under a drain bias of 1 mV.


Published in:
2018 48th European Solid-State Device Research Conference (ESSDERC), 114-117
Presented at:
48th European Solid-State Device Research Conference - ESSDERC 2018, 3-6 Sept. 2018 , Dresden, Germany
Year:
Oct 11 2018
Publisher:
IEEE
ISBN:
978-1-5386-5401-9
Laboratories:


Note: The status of this file is: Anyone


 Record created 2020-01-24, last modified 2020-04-20

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