High Speed SAR ADC Architectures in 28nm FDSOI CMOS

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, designing high performance analog functions has become difficult. Therefore the Successive Approximation Register (SAR) architecture has been improved because of its digital-like behaviour and reaches very high sampling rates above 1GS/s. Many speed enhancement techniques used in SAR ADCs were compatible for low-to medium resolution, up to 8-bit generally. Increasing the resolution adds different constraints that make drop the speed of the ADC considerably. The reasons for this speed drop are mainly the growing size of the Capacitive Digital to-Analog Converter (CDAC) which makes capacitor settling longer. On the other hand, comparator's noise and offset limits the accuracy as well. Combining both resolution and speed is then a difficult task to manage with conventional SAR ADC architectures. By using the different existing techniques, a high speed 10-bit SAR ADC has been targetted in 28nm FDSOI CMOS. A first version achieving 500MS/s has been designed. Alternate comparators and asynchronous logic were used to speed up the conversion rate. The CDAC has been kept small thanks to fractional reference voltages and capacitors in series. A two-step calibration method has been proposed in this first version to have a large range and fine tuning by using body-biasing technique. The ADC has been operational during measurements however a low accuracy has been obtained. A second version has been designed with an increased speed to 750MS/s and a more compact area. Custom fringe capacitors were used in this case and an offset calibration that averages also the noise. Measurements have shown a Signal to Noise and Distortion ratio that decreases considerably with the sampling rate. A 16x interleaved ADC has been designed based on the second version of the SAR ADC. The total sampling rate is then 12GS/s while its input bandwidth is 6GHz. A Delay Locked Loop (DLL) is used to generate the 16 clock phases. A full system with digital calibration and JESD204B compliant outputs is taped-out. The chip dimensions were 2mmx2mm. Additionally to these three tape-outs, different architectures enabling high speed operations with an enhanced resolution are presented. One technique consists in using an CDAC to compute the first 3 Most Significant Bits (MSBs) rapidly. Sampling rate of 800MSPS was simulated for a 10-bit ADC using this configuration. A second hybrid architecture combines standard CDAC conversions with comparator threshold configuring. The idea consists in obtaining the Least Significant Bits (LSBs) by varying the threshold of the comparators. This way, the CDAC in the front-end remains small and high bandwidth with high sampling rate could be obtained. A 9-bit SAR ADC achieving 1.3GS/s was simulated with this technique. Lastly, a pipelined speed enhancement technique of this hybrid architecture is proposed achieving 1.8GS/s with 8-bit resolution.


Advisor(s):
Leblebici, Yusuf
Year:
2019
Publisher:
Lausanne, EPFL
Keywords:
Laboratories:
LSM


Note: The status of this file is: EPFL only


 Record created 2019-12-09, last modified 2020-04-20

Fulltext:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)