Details
Title
Lee, Siang-Yun
Sciper ID
306917
Affiliated labs
LSI1
Publications
A Simulation-Guided Paradigm for Logic Synthesis and Verification
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits
Cost-generic Resubstitution Algorithm with Customizable Cost Functions
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization
Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition
Majority-based Design Flow for AQFP Superconducting Family
Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Technology-Aware Logic Synthesis for Superconducting Electronics
See complete list of publications (14)
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits
Cost-generic Resubstitution Algorithm with Customizable Cost Functions
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization
Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition
Majority-based Design Flow for AQFP Superconducting Family
Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
Technology-Aware Logic Synthesis for Superconducting Electronics
See complete list of publications (14)
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