000268329 001__ 268329
000268329 005__ 20190812204805.0
000268329 0247_ $$a10.1007/978-3-030-23696-0_16$$2doi
000268329 037__ $$aCONF
000268329 245__ $$aSix Shades of AES
000268329 260__ $$c2019
000268329 269__ $$a2019
000268329 336__ $$aConference Papers
000268329 520__ $$aRecently there have been various attempts to construct light weight implementations of the AES-128 encryption and combined encryption/ decryption circuits. However no known lightweight circuit exists forAES-192 and AES-256, the variants of AES that use longer keys. Investing in lightweight implementations of these ciphers is important as we enter the post quantum era in which security is, by a rule of the thumb, scaled down to the square-root of the size of the keyspace. In this paper, we propose a single circuit that is able to offer functionalities of both encryption and decryption for AES-128/192/256. Our circuit operates on an 8-bit datapath and occupies around 3672 GE of area in silicon. We outline the challenges that presented themselves while performing the combinatorial optimization of circuit area and the methods we used to solve them.
000268329 6531_ $$aAES
000268329 6531_ $$aEfficient implementation
000268329 6531_ $$aCircuit design
000268329 700__ $$g266837$$aBalli, Fatih
000268329 700__ $$aBanik, Subhadeep$$g283270
000268329 7112_ $$aProgress in Cryptology – AFRICACRYPT 2019
000268329 773__ $$tLecture Notes in Computer Science$$j11627$$q311-329
000268329 8560_ $$ffatih.balli@epfl.ch
000268329 8564_ $$uhttps://infoscience.epfl.ch/record/268329/files/aes.pdf$$s362727
000268329 909C0 $$pLASEC$$mfatih.balli@epfl.ch$$0252183$$zGrolimund, Raphael$$xU10433
000268329 909CO $$pconf$$pIC$$ooai:infoscience.epfl.ch:268329
000268329 960__ $$afatih.balli@epfl.ch
000268329 961__ $$afantin.reichler@epfl.ch
000268329 973__ $$aEPFL$$rREVIEWED
000268329 980__ $$aCONF
000268329 981__ $$aoverwrite