The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Moore’s law. Modern digital integrated circuits contain billions of transistors, fabricated with CMOS technology. As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. Among the materials that are studied for charge-based devices, two-dimensional materials of the Transition Metal Di-Chalcogenides (TMDCs) family show promising opportunities, thanks to their electrical and physical properties. In order to enable 2D electronics to be integrated in the Back-End-Of-the-Line (BEOL) with conventional CMOS it is essential to attain complementary operation of the transistors, in order to achieve low standby power consumption. In CMOS, ions are physically implanted in silicon to create unipolar devices with Ohmic contacts. However, this process requires high annealing temperatures, which are not compatible with the low-thermal budget requirements for monolithic 3D integration. For 2D materials, physical doping, through ion-implantation, has not proven to be successful due to extreme thinness of the 2D semiconductors. The possibility of introducing dopant atoms during growth of the 2D material has been reported, but does not allow for any control of the doping profile. Several chemical and molecular doping techniques have been developed, but are non-stable and non-CMOS compatible. A device concept that does not rely on any physical or chemical doping, and use instead un-doped materials, would be of great interest in this regard. In this thesis, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer tungsten di-selenide. We show how modulation of the Schottky barriers at drain and source by a separate gate, named polarity gate, can enable the selection of the carriers injected in the channel, and achieve controllable polarity behaviour with ON/OFF current ratios > 1E6 for both electrons and holes conduction. Following this demonstration, we fabricate and characterize a variety of polarity-controllable logic gates such as Inverter, NAND, NOR, that are the building primitives used in the logic synthesis frameworks for conventional CMOS logic. Moreover, we experimentally show 2- and 3-Input XOR, and majority gates that, thanks to the polarity-controllable devices, can be realized with fewer transistors as compared to what is achievable in conventional CMOS. We demonstrate a complete standard cell library with the possibility of fabricating compact, highly-expressive logic gates that can be exploited to gain advantages at circuit level, using XOR and MAJ functions as logic primitives. Moreover, for the first time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono and bi-layer 2D materials. Using ballistic self-consistent quantum simulations combined with TCAD simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to sub-10nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices.