Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84 x and 3.67 x, respectively, compared to VPR's single threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67 x and 5.46 x, while sacrificing the guarantee of reproducible results.


Published in:
2018 28Th International Conference On Field Programmable Logic And Applications (Fpl), 21-25
Presented at:
28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, IRELAND, Aug 26-31, 2018
Year:
Jan 01 2018
Publisher:
New York, IEEE
ISSN:
1946-1488
ISBN:
978-1-5386-8517-4
Laboratories:




 Record created 2019-06-18, last modified 2019-10-29

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