3D-Stacked CMOS SPAD Image Sensors: Technology and Applications

3Dstacked CMOS SPAD based image sensors hold the promise for better sensitivity and more functionality per pixel. The technology enables to separate detection from computation onto different chips, or tiers, that are stacked onto one another. One advantage is to be able to independently optimize detection and processing in dedicated processes. Another is to achieve extremely low skews across large chips, thus enabling accurate timing over multi-megapixel image sensors. A further advantage is the potential of implementing advanced functionality requiring large arrays of computational units directly connected with the detectors, thus paving the way to onchip convolutional neural networks and deep learning engines. In this paper we review several technologies enabling this interesting evolution and examples of possible implementations in the context of actual applications.


Publié dans:
2018 25Th Ieee International Conference On Electronics, Circuits And Systems (Icecs), 1-4
Présenté à:
25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, FRANCE, Dec 09-12, 2018
Année
Jan 01 2018
Publisher:
New York, IEEE
ISBN:
978-1-5386-9562-3
Mots-clefs:
Laboratoires:




 Notice créée le 2019-06-18, modifiée le 2019-12-05


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