Bridging the latency gap between NVM and DRAM for latency-bound operations

Non-Volatile Memory (NVM) technologies exhibit 4× the read access latency of conventional DRAM. When the working set does not fit in the processor cache, this latency gap between DRAM and NVM leads to more than 2× runtime increase for queries dominated by latency-bound operations such as index joins and tuple reconstruction. We explain how to easily hide NVM latency by interleaving the execution of parallel work in index joins and tuple reconstruction using coroutines. Our evaluation shows that interleaving applied to the non-trivial implementations of these two operations in a production-grade codebase accelerates end-to-end query runtimes on both NVM and DRAM by up to 1.7× and 2.6× respectively, thereby reducing the performance difference between DRAM and NVM by more than 60%.


Published in:
Proceedings of the 15th International Workshop on Data Management on New Hardware
Presented at:
International Workshop on Data Management on New Hardware (DaMoN’19), Amsterdam, Netherlands, July 1, 2019
Year:
Jul 01 2019
Publisher:
New York, NY, USA, ACM
ISBN:
978-1-4503-6801-8/19/07
Keywords:
Laboratories:




 Record created 2019-05-17, last modified 2019-05-24

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