Mixed-precision architecture based on computational memory for training deep neural networks

Deep neural networks (DNN) have revolutionized the field of machine learning by providing unprecedented human-like performance in solving many real-world problems such as image or speech recognition. Training of large DNNs, however, is a computationally intensive task, and this necessitates the development of novel computing architectures targeting this application. A computational memory unit where resistive memory devices are organized in crossbar arrays can be used to store the synaptic weights in their conductance states. The expensive multiply accumulate operations can be performed in place using Kirchhoff's circuit laws in a non-von Neumann manner. However, a key challenge remains the inability to alter the conductance states of the devices in a reliable manner during the weight update process. We propose a mixed-precision architecture that combines a computational memory unit storing the synaptic weights with a digital processing unit and an additional memory unit that stores the accumulated weight updates in high precision. The new architecture delivers classification accuracies comparable to those of floating-point implementations without being constrained by challenges associated with the non-ideal weight update characteristics of emerging resistive memories. The computational memory unit in a two layer neural network realized using non-linear stochastic models of phase-change memory achieves a test accuracy of 97.40% in the MNIST digit classification problem.

Published in:
2018 Ieee International Symposium On Circuits And Systems (Iscas)
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018
Jan 01 2018
New York, IEEE

 Record created 2018-12-13, last modified 2019-08-12

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