Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pith at a supply voltage of 0.8 V. The VD, implemented in an experimental chip fabricated in 14-nm CMOS FINFET, exploits set-partitioning principles and embedded per-survivor decision feedback to reduce implementation complexity and power consumption. The active area of the VD with 12 slices, each operating at one-eighth of the modulation rate, is 0.507 x 0.717 mm(2). Experimental results showing system performance are obtained by using a (2(15)-1)-bit pseudo-random binary sequence. The impact of the synchronization length and survivor path memory length on the detector design and system performance are shown. A new pipelined reduced-state sequence detector algorithm is presented for high-speed implementations. A novel speculative symbol timing recovery scheme is proposed. New simulation results are obtained to compare the performance of the Reed-Solomon (RS)-encoded 4-PAM scheme with that of the concatenated RS 4-D 5-PAM trellis-coded-modulation (TCM) scheme over an ideal band-limited additive-white-Gaussian-noise channel. Drawing on the results achieved for the VD, novel design techniques for a high-speed low-complexity eight-state 4-D 5-PAM TCM decoder is proposed.


Publié dans:
Ieee Transactions On Circuits And Systems I-Regular Papers, 65, 10, 3529-3542
Année
Oct 01 2018
Publisher:
Piscataway, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN:
1549-8328
1558-0806
Mots-clefs:
Laboratoires:




 Notice créée le 2018-12-13, modifiée le 2019-12-05


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