A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
2018
Details
Title
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
Author(s)
Giterman, R ; Fish, A ; Burg, A ; Teman, A
Published in
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume
65
Issue
4
Pages
1245-1256
Date
2018
Other identifier(s)
View record in Web of Science
Laboratories
TCL
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > TCL - Telecommunications Circuits Laboratory
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Record creation date
2018-11-08