Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analogto-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.


Presented at:
Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, Florence, Italy, 27-30 May 2018
Year:
May 04 2018
ISBN:
978-1-5386-4881-0
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Note: The status of this file is: EPFL only


 Record created 2018-06-10, last modified 2018-06-12

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