Details
Title
Burg, Andreas Peter
Sciper ID
194090
Affiliated labs
TCL
Publications
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems
Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers
Hardware Decoders for Polar Codes: An Overview
Hardware Implementation of Neural Self-Interference Cancellation
Logic-Compatible Multilevel Gain-Cell-Based DRAM for VLSI-SoCs
Low Power LDPC Decoding by Reliable Voltage Down-Scaling
Method and apparatus for low complexity spectral analysis of bio-signals
Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems
See complete list of publications (218)
Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems
Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers
Hardware Decoders for Polar Codes: An Overview
Hardware Implementation of Neural Self-Interference Cancellation
Logic-Compatible Multilevel Gain-Cell-Based DRAM for VLSI-SoCs
Low Power LDPC Decoding by Reliable Voltage Down-Scaling
Method and apparatus for low complexity spectral analysis of bio-signals
Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems
See complete list of publications (218)
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Burg, A.
Burg, Andreas
Burg, Andreas
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