Details
Title
Rana, Vincenzo
Sciper ID
182298
Affiliated labs
ESL
Publications
A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices
A High–Performance Parallel Implementation of the Chambolle Algorithm
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks
Island-Based Adaptable Embedded System Design
Knowledge-based design space exploration of wireless sensor networks
Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices
Run-Time Mapping for Dynamically-Added Applications in Reconfigurable Embedded Systems
See complete list of publications (16)
A High–Performance Parallel Implementation of the Chambolle Algorithm
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks
Island-Based Adaptable Embedded System Design
Knowledge-based design space exploration of wireless sensor networks
Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices
Run-Time Mapping for Dynamically-Added Applications in Reconfigurable Embedded Systems
See complete list of publications (16)
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