Notice détaillée
Titre
Beanato, Giulia
Sciper ID
188027
Publications
3D serial TSV link for low-power chip-to-chip communication
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory
3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling
A 3D Stacked Multi-Core Processor Platform with Improved Testability
Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors
Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs
Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology
Voir toutes les publications (12)
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory
3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling
A 3D Stacked Multi-Core Processor Platform with Improved Testability
Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors
Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs
Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology
Voir toutes les publications (12)
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