Notice détaillée
Titre
Pavlidis, Vasileios
Sciper ID
188258
Publications
3.5-D Integration: A Case Study
Clock and Power Distribution Networks for 3-D ICs
Enhanced Wafer Matching Heuristics for 3-D ICs
Inter-Plane Communication Methods for 3-D ICs
Power Distribution Paths for 3-D IC
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise
Voltage Propagation Method for 3-D Power Grid Analysis
Clock and Power Distribution Networks for 3-D ICs
Enhanced Wafer Matching Heuristics for 3-D ICs
Inter-Plane Communication Methods for 3-D ICs
Power Distribution Paths for 3-D IC
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise
Voltage Propagation Method for 3-D Power Grid Analysis
Employé pour
Pavlidis, V
Pavlidis, V F
Pavlidis, V.F.
Pavlidis, V F
Pavlidis, V.F.
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