000234345 001__ 234345
000234345 005__ 20190812210011.0
000234345 037__ $$aCONF
000234345 245__ $$aInverse Gating for Low Energy Block Ciphers
000234345 269__ $$a2018
000234345 260__ $$c2018
000234345 336__ $$aConference Papers
000234345 520__ $$aIn this paper we explore the technique of “inverse gating” which is a significant improvement over the ”round gating” technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit element to the next. Inverse gating generates the same timing signals required to segregate transient round signals, in a manner that incurs less delay and hence lesser switching activity in the circuits. We also show that energy-wise, inverse gated circuits outperform round gated circuits by a margin of around 30 %. In the second part of the paper, we further explore the efficiency of the energy reduction by tuning some of the design parameters. The most natural candidate for this was the delay of the buffer used for creating the timing signals. We found that the optimal energy consumption for any round and inverse gated unrolled block cipher occurs at a particular range of this delay value. We try to explain the optimality of this particular choice of design parameter with the help of the implementation of the AES-128 block cipher.
000234345 700__ $$0250951$$g283270$$aBanik, Subhadeep
000234345 700__ $$aBogdanov, Andrey
000234345 700__ $$aIsobe, Takanori
000234345 700__ $$aHiwatari, Harunaga
000234345 700__ $$aAkishita, Toru
000234345 700__ $$aRegazzoni, Francesco$$0(EPFLAUTH)176424$$g176424
000234345 7112_ $$aIEEE International Symposium on Hardware Oriented Security and Trust
000234345 909C0 $$xU10433$$pLASEC$$0252183
000234345 909CO $$pconf$$pIC$$ooai:infoscience.tind.io:234345
000234345 917Z8 $$x266837
000234345 937__ $$aEPFL-CONF-234345
000234345 973__ $$rREVIEWED$$sACCEPTED$$aEPFL
000234345 980__ $$aCONF