A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic-in-Memory (PLiM) computer has been proposed operating on an RRAM memory array and an instruction set to access the in-memory capabilities of the RRAM cells. Since the RRAM’s intrinsic logic operation is based on the majority-of-three function, Majority Inverter Graphs (MIGs) can be used to implement a compiler that translates Boolean functions into PLiM instructions. This work presents a fast MIG-based PLiM compiler aiming at parallelizing RRAM instructions under resource constraints. Considering valid the assumption that all RRAM cells in the PLiM computer can be enabled in parallel, helps evaluating the theoretical potential of the PLiM parallelization as part of a larger architecture exploration effort. More complex scenarios can easily be adapted by our approach. The code is optimized to reduce number of accesses to the memory and its structure enables a very low runtime compared to the state-of-the-art approach. Resource constraints allow to fit the PLiM instructions into a given maximum number of RRAM cells.


Published in:
Proceedings of the 26th International Workshop on Logic & Synthesis (IWLS)
Presented at:
26th International Workshop on Logic & Synthesis (IWLS), Austin, Texsas, USA, June 17-18, 2017
Year:
Jun 18 2017
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / SNF 200021-146600
Laboratories:




 Record created 2018-01-09, last modified 2018-11-26

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