000233721 001__ 233721
000233721 005__ 20190317000910.0
000233721 020__ $$a978-1-5386-3093-8
000233721 0247_ $$a10.1109/ICCAD.2017.8203799$$2doi
000233721 037__ $$aCONF
000233721 245__ $$aEnabling exact delay synthesis
000233721 260__ $$c2017-11-16$$bIEEE
000233721 269__ $$a2017-11-16
000233721 336__ $$aConference Papers
000233721 500__ $$aERC Cybercare 669354 / Grant 2016016 United States-Israel Binational Science Foundation
000233721 520__ $$aGiven (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the output(s). The exact delay synthesis problem, with given input arrival times, relates to computing the communication complexity of a Boolean function, which is an intractable problem. Input arrival times are variable and can take any value, thereby making the exact delay synthesis search space infinite. This paper presents theory and algorithms for exact delay synthesis. We introduce the theory of equioptimizable arrival times, which allows us to partition all arrival time patterns into a finite set of equivalence classes. Thanks to this new theory, we create for the first time exact delay circuit databases covering all Boolean functions up to 5 variables and all possible arrival time patterns. We describe further arrival time compression techniques which enable the creation of larger databases. We propose an enhanced delay synthesis flow capable of dealing with large circuits, combining exact delay logic rewriting and Boolean optimization techniques, attaining unprecedented results. We improve 9/10 of the best known results in the EPFL arithmetic delay synthesis competition, outperforming previous best results up to 3×. Embedded in a commercial EDA flow for ASICs, our exact delay synthesis techniques reduce the total negative slack by 12.17%, after physical implementation, at negligible area and runtime costs.
000233721 700__ $$aAmarù, Luca
000233721 700__ $$g263922$$aSoeken, Mathias$$0249604
000233721 700__ $$aVuillod, Patrick
000233721 700__ $$aLuo, Jiong
000233721 700__ $$aMishchenko, Alan
000233721 700__ $$aGaillardon, Pierre-Emmanuel
000233721 700__ $$aOlson, Janet
000233721 700__ $$aBrayton, Robert
000233721 700__ $$g167918$$aDe Micheli, Giovanni$$0240269
000233721 7112_ $$dNovember 13-16, 2017$$cIrvine, California, USA$$a36th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
000233721 773__ $$tProceedings of the 36th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
000233721 8560_ $$fcarole.burget@epfl.ch
000233721 8564_ $$uhttps://infoscience.epfl.ch/record/233721/files/2017_iccad.pdf$$zn/a$$s389398$$yn/a
000233721 909C0 $$xU11140$$0252283$$pLSI1
000233721 909CO $$pIC$$qGLOBAL_SET$$ooai:infoscience.tind.io:233721$$pconf$$pSTI
000233721 917Z8 $$x112915
000233721 917Z8 $$x112915
000233721 937__ $$aEPFL-CONF-233721
000233721 973__ $$rREVIEWED$$aEPFL
000233721 980__ $$aCONF