Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) and Spin Torque Majority Gates (STMG) are based on majority logic. In addition, technology constraints require to restrict the number of fan-outs or impose difficulties in realizing inversions. In this paper, we use a majority-based logic synthesis approach to synthesize inversion-free networks with restricted fan-out. We propose one algorithm that propagates all inversions to the primary inputs and another algorithm that limits the number of fan-outs of each majority gate. These algorithms show significant impact on QCA- and STMG-based circuits. Experimental results demonstrate that the average area-delay-energy product can be improved by 3.1× in QCA-based circuits and from 2.9× to 8.1× for STMG-based circuits.


Published in:
Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169
Presented at:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 3-5 July 2017
Year:
Jul 05 2017
Publisher:
IEEE
Keywords:
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / IC EPFL Fellowship
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2018-01-09, last modified 2018-09-13

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